1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to, e.g., a semiconductor memory device having a memory element which records information in accordance with a change in resistance value.
2. Description of the Related Art
In recent years, there are proposed a variety of solid-state memories which record information on the basis of a new principle. Of these proposals, a magnetic random access memory (MRAM) using the tunneling magnetoresistive (TMR) effect is attracting a great deal of attention as a solid-state magnetic memory. The characteristic feature of the MRAM is that it stores data in accordance with the magnetization state of a magnetic tunnel junction (MTJ) element.
In a conventional MRAM which writes data on the basis of a magnetic field generated by a current flowing to an interconnection, a reduction in the size of an MTJ element increases the coercive force. This often increases a current necessary for writing. It is therefore difficult for the conventional MRAM to satisfy both the micropatterning of cells and the decrease in current consumption aiming at an increase in capacity.
To overcome this drawback, a spin-injection-type MRAM using a spin momentum transfer (SMT) write scheme is proposed. The spin-injection-type MRAM writes data on the basis of a current flowing to an MTJ element in a direction perpendicular to the film plane, and changes the spin direction of a free layer in accordance with the direction of this current. One memory cell includes one MTJ element and one selection transistor. For example, this selection transistor shares a source region with its adjacent cell to reduce the cell area.
Assume, however, that two selection transistors share a source region in the spin-injection-type MRAM. To supply the source potential via an interconnection, there are available two methods, i.e., (1) a method of arranging a source potential interconnection parallel to the gate electrodes of the selection transistors, and (2) a method of arranging a source potential interconnection in a direction perpendicular to the gate electrodes of the selection transistors. In (2), on an active area arranged perpendicular to the gate electrodes of the selection transistors, a contact cannot be directly formed in the source region of the selection transistors from the source potential interconnection.
A related technique of this type has been disclosed, which decreases the number of interconnections by arranging MRAM cells such that one write word line is necessary for every two word lines while one ground line is necessary for every two bit lines (see Jpn. Pat. Appln. KOKAI Publication No. 2005-191523).